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MPC89X54A 8-bit micro-controller this document contains information on a new product under devel opment by megawin. megawin reserves the right to change or disco ntinue this product without notice. ? megawin technology co., ltd. 2008 all rights reserved. 2008/12 version a12 megawin features ............................................................................................................................... ... 2 general description ............................................................................................................... 3 order information: ................................................................................................................. 3 pin description....................................................................................................................... 4 pin definition ................................................................................................................. 4 pin configuration ........................................................................................................... 6 block diagram ....................................................................................................................... 6 special function register ...................................................................................................... 8 memory ............................................................................................................................... ... 9 organization ................................................................................................................... 9 nonvolatile registers: .................................................................................................. 10 ram ............................................................................................................................ 11 embedded flash ........................................................................................................... 12 functional description ......................................................................................................... 13 timers/counters ................................................................................................. 13 timer0 (t0) and timer1 (t1) ...................................................................... 15 timer2 ............................................................................................................... 16 interrupt ........................................................................................................................ 20 watchdog timer ........................................................................................................... 22 serial io port (uart) ................................................................................................. 23 reset ............................................................................................................................. 26 power saving mode and pof ...................................................................................... 26 in system programming (isp) ..................................................................................... 27 in-application program ............................................................................................... 31 note for other sfr ...................................................................................................... 32 absolute maximum rating (mpc89e54a) ........................................................................ 33 dc characteristics (mpc89e54a) ...................................................................................... 33 absolute maximum rating (mpc89l54a) ........................................................................ 34 dc characteristics (mpc89l54a) ...................................................................................... 34 package dimension .............................................................................................................. 35 revision history .................................................................................................................. 38
features z 80c51 central processing unit z 16kb on-chip program memory z isp capability; optional 1kb/2kb/4kb isp memory shared with data flash memory. z iap capability; up to 47 k bytes programmable data flash available shared with isp memory. z on-chip 256 bytes scratch-pad ram and 1024 byte s auxiliary ram; be capable of addressing up to 64 k bytes external memory z movc-disabling, encrypting, and locking fl ash memory realize security mechanism. z three 16-bits timer/counter, timer2 is an up/down counter with programmable clock output on p1.0 z eight sources, four-level-p riority interrupt capability z enhanced uart, provides frame-error detection and hardware address-recognition z dual dptr for fast-accessing of data memory z 15 bits watch-dog-timer with 8-bit pre-scalar, one-time enabled z power control: idle mode and power-down mode; power-down can be woken-up by p3.2/p3.3/p4.2/p4.3 z low emi: inhibit ale emission z four 8-bits bi-directional ports; extra four-bit additional p4 are available for plcc-44 and pqpf-44 z on-chip flash program/data memory: - the data endurance of the embedded flash gets over 20,000 times. - greater than 100 years data rentention under room temperature operating voltage: - 4.5v~5.5v for mpc89e54a - 2.4v~3.6v for mpc89l54a, minimu m 2.7v requirement in flash write operation (isp/icp/?...) - built-in low-voltage-reset circuit. z operating temperature - industrial (-40c to +85c)* z maximum operating frequency: - optional 12t or 6t mode - up to 48mhz@12t or 24mhz@6t, industrial range z three package types: - pdip 40: MPC89X54Ae - plcc 44: MPC89X54Ap - pqfp 44: MPC89X54Af *: tested by sampling 2 MPC89X54A data sheet megawin
general description pc89x54a is a single-chip 8-bit microcontroller with the instruction sets fully compatible with industrial-standard 80c51 series microcontroller. there is 16 kbytes flash memory embedded for application program. a 47 kbytes data flash is shared by both in-system programming code and in-application-programming code. in-system-programming and in-application-programming allow the users to download new code or data while the microcontroller sits in the running state. there are 1280 bytes on-chip ram embedded th at are provided to implement wide field applications. the user can configure the device to run in 12 clocks per machine cycle, or 6 clocks per machine cycle to achieve twice performance. MPC89X54A is built with four 8-bit i/o ports, one 4-bit i/o ports, three 16-bit timer/counters, an eight-source, four-priority-level interrupt structure, an enhanced uart, and on-chip crystal oscillator. it was fabricated in advanced embedded flash cmos technology. excellent flash-endurance, flash-retent ion, and code-protecting security make MPC89X54A as an excellent microcontroller. if the supply voltage of the device is lower than 3.7v/2.4v (operate in the 5v/3v).the device can automatically go to reset, and we have named the low-voltage-reset order information: part number temperature range package packing operation voltage x : (l/e) MPC89X54Ae industrial pdip-40 tube l:3v / e:5v MPC89X54Ap industrial plcc-44 tube l:3v / e:5v MPC89X54Af industrial pqfp-44 tube l:3v / e:5v megawin MPC89X54A data sheet 3
pin description pin definition pin number pin name dip-40 plcc-44 pqfp-44 type description p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) 39 38 37 36 35 34 33 32 43 42 41 40 39 38 37 36 37 36 35 34 33 32 31 30 b port0 is an open-drain, bi-directional io port. when 1 s are written to port0, they become high-impedance inputs. port0 is also multiplexed with low-order address or data bus during accesses to external program and data memory. p1.0 (t2) p1.1 (t2ex) p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 9 40 41 42 43 44 1 2 3 bu general-purposed i/o with weak pull-up resistance inside. when 1 s are written into port1, the strong output driving pmos only turn-on two clock periods and then the weak pull-up resistance keep the port high. p1.0 is also used as one of event sources for timer2, or output carrier of timer2, alias t2. p1.1 is also used as one of interrupt-controlling sources for time2, alias t2ex. p2.0 (a8) p2.1 (a9) p2.2 (a10) p2.3 (a11) p2.4 (a12) p2.5 (a13) p2.6 (a14) p2.7 (a15) 21 22 23 24 25 26 27 28 24 25 26 27 28 29 30 31 18 19 20 21 22 23 24 25 bu port2 is an 8-bit bi-directional i/o port with pull-up resistance. except being as gpio, port2 emits the high-order address byte during accessing to external program and data memory. p3.0 (rxd) p3.1 (txd) p3.2 (int0) p3.3 (int1) p3.4 (t0) 10 11 12 13 14 11 13 14 15 16 5 7 8 9 10 bu general-purposed i/o with weak pull-up resistance inside. when 1 s are written into port1, the strong output driving pmos only turn-on two clock periods and then the weak pull-up resistance 4 MPC89X54A data sheet megawin
p3.5 (t1) p3.6 (/wr) p3.7 (/rd) 15 16 17 17 18 19 11 12 13 keep the port high. port3 also serves other special functions of this device. p3.0 and p3.1 act as receiver and transceiver of the data for uart function block, alias rxd and txd. p3.2 and p3.3 also act as external interrupt sources, alias int0 and int1. p3.4 and p3.5 also act as event sources for timer0 and timer1 individually, alias t0 and t1. p3.6 also acts as write signal while access to external memory, alias /wr. p3.7 also acts as read signal while access to external memory, alias /rd. p4.0 p4.1 p4.2 (/int3) p4.3 (/int2) 23 34 1 12 17 28 39 6 bu port4 is extended i/o ports such like port1. it can be available only on 44l-plcc and 44l-pqfp package. reset 9 10 4 is a high on this pin for at least two machine cycles will reset the device. ale 30 33 27 o output pulse for latching the low byte of address during accesses to external memory. /psen 29 32 26 o the read str obe to external program memory, low active. /ea 31 35 29 i ea must be kept at low to enable the device to fetch program code from external flash memory. an internal pull-up resistance has been embedded in this pin. xtal1 19 21 15 i input to the inverting oscillator amplifier. xtal2 18 20 14 o output from the inverting amplifier. vdd 40 44 38 p power supply vss 20 22 16 g ground megawin MPC89X54A data sheet 5
pin configuration 1 2 3 20 18 17 4 5 6 7 8 9 16 15 10 11 12 13 14 19 21 23 24 25 26 30 29 28 27 22 31 33 34 35 36 40 39 38 37 32 (t2) p1.0 (t2ex) p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 p1.7 reset (rxd) p3.0 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 (t1) p3.5 (/wr) p3.6 (/rd) p3.7 xtal2 xtal1 vss vdd p0.0 (ad0) p0.1 (ad1) p0.2 (ad2) p0.3 (ad3) p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) /ea ale /psen p2.7 (a15) p2.6 (a14) p2.5 (a13) p2.4 (a12) p2.3 (a11) p2.2 (a10) p2.1 (a9) p2.0 (a8) 1 2 17 44 39 p1.5 p1.6 p1.7 reset (rxd) p3.0 (/int2) p4.3 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) /ea ale /psen p2.7 (a15) p2.5 (a13) 40 6 29 28 16 p3.6 (/wr) 7 8 9 10 11 12 13 14 15 18 19 20 21 22 23 24 25 26 27 30 31 32 33 34 35 36 37 38 41 42 43 3 4 5 p1.4 p1.3 p1.2 (t2ex) p1.1 (t2) p1.0 (int3) p4.2 vdd (ad0) p0.0 (ad1) p0.1 (ad2) p0.2 (ad3) p0.3 p3.7 (/rd) xtal2 xtal1 vss p4.0 p2.0 (a8) p2.1 (a9) p2.2 (a10) p2.3 (a11) p2.4 (a12) p2.6 (a14) (t1) p3.5 MPC89X54Ap (plcc-44) 39 40 11 38 33 p1.5 p1.6 p1.7 reset (rxd) p3.0 (/int2) p4.3 (txd) p3.1 (int0) p3.2 (int1) p3.3 (t0) p3.4 p0.4 (ad4) p0.5 (ad5) p0.6 (ad6) p0.7 (ad7) /ea p4.1 ale /psen p2.7 (a15) p2.5 (a13) 34 44 23 22 10 p3.6 (/wr) 1 2 3 12 13 14 15 16 17 18 19 20 21 24 25 26 27 28 29 30 31 32 35 36 37 41 42 43 p1.4 p1.3 p1.2 (t2ex) p1.1 (t2) p1.0 (int3) p4.2 vdd (ad0) p0.0 (ad1) p0.1 (ad2) p0.2 (ad3) p0.3 p3.7 (/rd) xtal2 xtal1 vss p4.0 p2.0 (a8) p2.1 (a9) p2.2 (a10) p2.3 (a11) p2.4 (a12) p2.6 (a14) (t1) p3.5 4 5 6 7 8 9 MPC89X54Ae ( pdip-40 ) MPC89X54Af (pqfp-44) p4.1 block diagram 6 MPC89X54A data sheet megawin
ram addr register ram256 port0 latch port2 latch flash rom isp address generator program counter dptr port0 driver port2 driver b register acc tmp2 tmp1 alu stack pointer timer0/1 timer2 uart psw wdt port3 latch port1 latch port4 latch port3 driver port1 driver port4 driver control unit p2.0 ~ p2.7 p0.0 ~ p0.7 p1.0 ~ p1.7 p3.0 ~ p3.7 p4.0 ~ p4.3 psen ale ea reset MPC89X54A block diagram xtal1 xtal2 eram megawin MPC89X54A data sheet 7
special function register f8 f0 b e8 p4 e0 acc wdtcr ifd ifadrh ifadrl ifmt scmd ispcr d8 d0 psw c8 t2con t2mod rcap2l rcap2h tl2 th2 c0 xicon b8 ip saden b0 p3 iph a8 ie saddr a0 p2 auxr1 98 scon sbuf 90 p1 reserved 88 tcon tmod tl0 tl1 th0 th1 auxr 80 p0 sp dpl dph pcon symbol description initial value p0 port 0 11111111b sp stack pointer 00000111b dpl data pointer low 00000000b dph data pointer high 00000000b pcon power control smod smod0 - pof gf1 gf0 pd idl 01110000b tcon timer control tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 00000000b tmod timer mode gate c//t m1 m0 gate c//t m1 m0 00000000b tl0 timer low 0 00000000b tl1 timer low 1 00000000b th0 timer high 0 00000000b th1 timer high 1 00000000b auxr auxiliary eram ao xxxxx00b p1 port 1 t2ex t2 11111111b scon serial control sm0 /fe m1 sm2 ren tb8 rb8 ti ri 00000000b sbuf serial buffer xxxxxxxxb p2 port 2 11111111b auxr1 auxiliary 1 gf2 dps xxxx0xx0b ie interrupt enable ea et2 es et1 ex1 et0 ex0 00000000b saddr slave address 00000000b p3 port 3 rd wr t1 t0 int1 int0 txd rxd 11111111b iph interrupt priority high px3h px2h pt2h psh pt1h px1h pt0h px0h x0000000b ip interrupt priority low pt2 ps pt1 px1 pt0 px0 x0000000b saden slave address mask 00000000b xicon external interrupt control px3 ex3 ie3 it3 px2 ex2 ie2 it2 t2con timer 2 control tf2 exf2 rclk tclk exen2 tr2 c/t2 cp/rl 00000000b t2mod timer2 mode t2oe dcen xxxxxx00b rcap2l timer2 capture low 00000000b rcap2h timer2 capture high 00000000b tl2 timer low 2 00000000b th2 timer high 2 00000000b psw program status word cy ac f0 rs1 rs0 ov - p 00000000b acc accumulator 00000000b wdtcr watch-dog-timer control register - - enw clw widl ps2 ps1 ps0 xx000000b ifd isp flash data 11111111b ifadrh isp flash address high 00000000b ifadrl isp flash address low 00000000b ifmt isp mode table - - - - - ms2 ms1 ms0 xxxxx000b scmd isp serial command xxxxxxxxb ispcr isp control register ispen bs srst - - ick2 ick1 ick0 000xx000b p4 port 4 - - - - ebh eah e9h e8h xxxx1111b b b register 00000000b 8 MPC89X54A data sheet megawin
memory organization address space for MPC89X54A ram 00-7f ram, access it via direct addressing 80-ff sfr, access it via direct addressing 80-ff indirect on-chip ram, access it via indirect addressing 0000-03ff on-chip expanded ram (1024b), access it via movx instruction 0000- off-chip memory, enabled by setting eram 00 80 03ff 7f ff 0000-3fff program memory (16kb) 4000-fbff nonvolatile data memory shared with isp program memory. isp program could take 1kb, 2kb or 4kb depending on or0[5:4] 0000 4000 3fff fbff address space for MPC89X54A embedded flash memory bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ispas1 ispas0 - movcl sb lock non-volatile register or0 7 6 5 4 3 2 1 0 fzwdtcr oscdn hwbs en6t non-volatile register or1 megawin MPC89X54A data sheet 9
nonvolatile registers: there are two nonvolat ile registers named or0 and or1 individually. they are designed to configure the MPC89X54A options. generally these two nonvolatile registers will be written via a popular nvm writer, i.e., hi-lo system all-11, leaper-48 and megawin-provided mc u writer. furthermore, the user can change the nvm register or1 by the isp program in a manner as same as writing the data flash , but or0 can only be written via an off-line popular nvm writer. nvm register: or0 ( option register 0 ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - ispas1 ispas0 - movcl sb lock { ispas1 , ispas0 }: used to identify the start address for isp program { 0, 0 }:= the isp space is from 0xec00 to 0xfbff (4k size). { 0, 1 }:= the isp space is from 0xf400 to 0xfbff (2k size). { 1, 0 }:= the isp space is from 0xf800 to 0xfbff (1k size) { 1, 1 }:= no isp space. these two bits decide where the isp program locates, and how the isp program and the data flash shares the 47k embedded flash. movcl : used to determine if movc instruction will be disabled. 0: = movc is conditionally disabled. 1: = movc is always available. sb : used to determine if the program code will be scrambled while it is dumped. 0: = code dump from writer is scrambled. 1: = code dump from writer is transparent. lock : used to determine if the program code wi ll be locked against the popular writer. 0: = lock code. 1: = does not lock code if the code is locked, all the data dum ped from a popular will always show ffh. please check file ?initial configuration.pdf ? to get the default value of the or0. 10 MPC89X54A data sheet megawin
nvm register: or1 ( option register 1 ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 fzwdtcr oscdn hwbs en6t fzwdtcr : used to freeze the wdt-controlling register. 0 :=configure the sfr wdtcr to be reset only via power-up action, not by software reset nor reset from the watch dog timer. 1: =(default) permit all the reset events from power-up, software and the watch dog timer could reset the sfr wdtcr . oscdn : used to adjust the behavior of crystal oscillator. 0: = the dc gained of crystal oscillator amplifier is doubled but bandwidth is reduced. it will bring help to emi reducing and improve the power cons umption. dealing with application does not need high frequency clock (under 20mhz), and it is recommended to do so. 1: = the gained of crystal oscillator is enough for o scillator to start oscillating up to 48 mhz. hwbs : used to configure the MPC89X54A boot from isp program or normal applic ation program after the power-on sequence. 0: = the MPC89X54A will boot from isp start address after power-on. 1:= no operation. the MPC89X54A will b oot from normal application program. en6t : used to configure the MPC89X54A run in 6t 12t mode or 6t mode. 0: = the MPC89X54A will run in 6t mode 1: = the MPC89X54A will run in 12t mode the default value of the or1 is ff h. ram there are 1280 bytes ram built in MPC89X54A. the user can visit the leading 128-byte ram vi a direct addressing inst ructions, we have named those ram as direct ram that occupies address space 00h to 7fh. followed 128-byte ram can be visited via indi rect addressing instructions, we have named those ram as indirect ram that occupied address space 80h to ffh. the other 1024-byte ram is named expanded ra m that still occupied address space 0000h to 03ffh. an user can access it via general register r i , or via data pointers dptr associated with movx instructions, say movx a, @r1 or movx a, @dptr . to reserve the natural characteristic of instruction movx which is designed to access exter nal memory, the user can set the bit eram in sfr auxr as 1, and by doing so is to hide the expanded ram and to visit the external memory. megawin MPC89X54A data sheet 11
embedded flash there is totally 63 k bytes flash embedded in the MPC89X54A. the leading 16 k bytes flash memory is designe d for storage of the user program, and followed 47 k bytes flash memory is shared with nonvolatile data flash and isp program. while the program counter of MPC89X54A is spanning over 3fffh, the device will fetch its program code from the external memory at once ignoring the /ea pin status. in that case, it will never fetch the program code from the following embedded flash. the user can develop the isp program and put it into the embedded flash that addressed from ec00h, f400h, or f800h by configuring or0 [5:4] . excluding the isp program, the remained flash spaces can be taken as data flash which can be read, even written by the application program or the isp program from the user. 12 MPC89X54A data sheet megawin
functional description timers/counters MPC89X54A has three 16-bit timers, and they are named t0 , t1 and t2 . each of them can also be used as a general event counter, which counts the transition from 1 to 0. while t0/t1/t2 is used as ?timer? function, the time unit that used to measure the timer is machine cycle . a machine cycle equals 12 or 6 oscillator periods, and it depends on 12t mode or 6t mode that the user configured this device. while t0/t1/t2 is used as ?1-0 event counter? function, the counting event is the ?high-to-low transition? of primitive pin t0/t1/t2 . in this mode, the device periodically samples the status of pin t0/t1/t2 once for each machine cycle. whenever the sampled result turns from 1 to 0, the device will count once on the counter. becarefu lly, this kind of implementation for the counter requires the high-duty or low-duty from pin t0/t1/t2 and must not too short compared to a machine cycle. there are two sfr designed to configure timers t0 and t1 . they are tmod , and tcon . there are extra two sfr designed to configure timer t2 . they are t2mod , and t2con. sfr : tmod bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 (for timer1 use) (for timer0 use) gate c//t m1 m0 gate c//t m1 m0 gate : gating control when set. if gate=1, timer/counter x is enabled only while ?/int x ? pin is high and ?tr x ? control bit is set. when cleared timer x is enabled whenever ?tr x? control bit is set. c//t : timer or counter function selector. 0 : =timer, 1 : =counter {m1, m0}: mode select {0, 0}: = 13-bit timer/coun ter for timer0 and timer1 {0, 1}: = 16-bit timer/coun ter for timer0 and timer1 {1, 0}: = 8-bit timer/counter with aut omatic reload for timer0 and timer1 {1, 1}: = for timer0: = tl0 is 8-bit time r/counter, th0 is locked into 8-bit timer for timer1:= timer/counter1 stopped megawin MPC89X54A data sheet 13
sfr : tcon bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 tf1 tr1 tf0 tr0 ie1 it1 ie0 it0 tf1 : = timer1 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the processor vectors to the interrupt routin e, or clearing the bit in software. tr1 : = timer1 run control bit. set/cleared by software. tf0 : = timer0 overflow flag. set by hardware on timer/counter overflow. cleared by hardware when the processor vectors to the interrupt rout ine, or clearing the bit in software. tr0 : = timer1 run control bit. set/cleared by software. ie1 : = interrupt 1 edge flag. set by hardware when exte rnal interrupt edge detected. cleared when interrupt processed. it1 : = interrupt 1 type control bit. set/cleared by software to specified falling edge/low level triggered interrupt. ie0 : = interrupt 0 edge flag. set by hardware when exte rnal interrupt edge detected. cleared when interrupt processed. it0 : = interrupt 0 type control bit. set/cleared by software to specified falling edge/low level triggered interrupt. sfr : t2mod bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t2oe dcen t2oe : timer 2 output enable bit. it enables ti mer2 overflow rate to toggle p1.0. dcen : down count enable bit. when set, this allows timer2 to be configured as a down counter. sfr : t2con bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 tf2 exf2 rclk tclk exen2 tr2 c//t2 cp/rl2 tf2 : timer2 overflow flag. it will be set by a timer2 overflow and must be cleared by software. tf2 will not be set when either tclk or rclk =1. exf2 :timer2 external flag. it will be set when either a ca pture or reload is caused by a negative transition on pin t2ex and exen2 =1. when timer2 interrupt is enabled, exf2 =1 will cause the cpu to vector to he timer2 interrupt routine. exf2 must be cleared by software. exf2 does not cause an interrupt in auto-reload up -down mode ( arud ). rclk : when set causes the serial port to use timer2 overflow pulse for its receive clock in mode and mode 3. rclk=0 causes timer1 overflow pulse to be used. tclk : when set causes the serial port to use timer2 ov erflow pulse for its transmit clock in mode 1 and mode 3. rclk =0 causes timer1 overflow pulse to be used. exen2 : timer-2 external enable flag. when set, allows a capture or reload to occur. as a result of a negative transition on t2ex if timer2 is not being used to clock the serial port. exen2 =0 causes timer2 to ignore events at t2ex . tr2 : start/stop control for timer2. 14 MPC89X54A data sheet megawin
c/t2 : timer or counter select. 0 is for timer and 1 is for external event counter. cp/rl2 : capture/reload flag. when set, captures will occurs on a negative transition at t2ex if exen2 =1. when cleared, auto-reloads will occur either with timer2 overflows or a negative transition at t2ex when exen2 =1. when whether tclk or rclk is 1, this bit is ignored and the timer is forced to auto-reload on timer2 overflow. timer0 (t0) and timer1 (t1) mode 0 the timer register is configured as a 13-bit register. as when the count rolls over from all 1s to all 0s, it sets the timer interrupt flag tfx . the counted input is enabled to the timer when trx = 1 and either gate=0 or intx = 1. mode 0 operation is the same for timer0 and timer1. mode 0 0 1 osc/12 t0 or t1 pin (sampled) 0 1 gate /int x tr x tlx [4:0] th x [7:0] tf x interrupt c/ / t mode 1 mode1 is the same as mode0, except that the timer register is being run with all 16 bits. mode 1 0 1 osc/12 t0 or t1 pin (sampled) 0 1 gate /int x tr x tlx [7:0] th x [7:0] tf x interrupt c/ / t mode 2 mode 2 configures the timer register as an 8-bit counter (tl x ) with automatic reload. overflow from tl x does not only set tf x , but also reloads tl x with the content of th x , which is determined by user?s program. the reload leaves th x unchanged. mode 2 operation is the same for timer0 and timer1. megawin MPC89X54A data sheet 15
0 1 osc/12 t0 or t1 pin ( sampled) 0 1 tlx [7:0] tfx interrupt mode 2 mode 3 timer1 in mode3 simply holds its count, the effect is the same as setting tr1 = 1. timer0 in mode 3 enables tl0 and th0 as two separate 8-bit counters. tl0 uses the timer0 control bits such like c/t, gate, tr0, int0 and tf0. th0 is locked into a timer function (can not be external event counter) and take over the use of tr1, tf1 from timer1. th0 now controls the timer1 interrupt. mode 3 timer2 timer2 is a 16-bit timer/counter which can operat e as either an event timer or an event counter as selected by c//t2 in the special function register t2con . timer2 has four operation modes: capture mode (cp), auto-reload up/down mode (arud), auto-reload up-only mode (aruo) and baud-rate generator mode (brg). logical or (rclk, tclk) cp/rl2 tr2 dcen mode x x 0 x off 1 x 1 0 baud-rate generation 0 1 1 0 capture 0 0 1 0 auto-reload up-only 0 0 1 1 auto-reload up/down timer2 mode table 0 1 osc/12 sampled t0 pin 0 1 gate /int0 tr0 tl0 [7:0] tf0 interrupt xtal2 0 1 th0 [7:0] tf1 interrupt tr1 c/ / t gate /intx trx c/ / t reload thx [7:0] 16 MPC89X54A data sheet megawin
timer2 is also can be configured as a periodical signal generator. the MPC89X54A is able to generate a programmable clock output on p1.0. when t2oe bit is set and c//t2 bit is cleared, timer2 overflow pulse will generate a 50% duty clock and output that to p1.0. the frequency of clock-out is calculated according to the following formula. oscillator frequency 4 x ( 65536 ? rcap2h , rcap2l ) in the clock-out mode, timer2 rollovers will not generate an interrupt. capture mode (cp) in the capture mode, timer2 is incremented by either osc/12 or external pin (t2) 1-to-0 transition. tr2 controls the event to timer2 and a 1-to-0 transition on t2ex pin will trigger rcap2h and rcap2l registers to capture the timer2 contents onto them if exen2 is set. an overflow in timer2 sets tf2 flag and a 1-to-0 tr ansition in t2ex pin sets exf2 flag if exen2=1. tf2 and exf2 is ored to request the interrupt service. 0 1 osc/12 t2 pin 0 1 tr2 tl2 [7:0] tf2 interrupt c//t2 th2[7:0] rcap2l [7:0] rcap2h [7:0] t2ex pin exen2 exf2 megawin MPC89X54A data sheet 17
auto-reload up-only mode (aruo) in aruo mode, timer2 can be configured to count up with a software-defined value to be reloaded. when reset is applied to the dcen =0 and cp/rl2=0, timer2 is at aruo mode. an overflow on timer2 or 1-to-0 transition on t2ex pin will load rcap2h and rcap2l contents onto timer2, also set tf2 and exf2, respectively. 0 1 osc/12 t2 pin 0 1 tr2 tl2 [7:0] tf2 interrupt c//t2 th2[7:0] rcap2l [7:0] rcap2h [7:0] t2ex pin exen2 exf2 auto-reload up-down mode (arud) in arud mode, timer2 can be configured to count up or down. when dcen =1 and cp/rl2=0, timer2 is at arud mode. the counting dire ction is determined by t2ex pin. if t2ex= 1 , counting up, otherwise counting down. an overflow on timer2 will set tf2 and toggle exf2. exf2 cannot generate interrupt request in this mode. if the counting direction is down, the overflow loads 0xffff onto timer2 and if counting direction is up, the overflow loads rcap2h, rcap2l contents onto timer2. 0 1 osc/12 t2 pin 0 1 tr2 tl2 [7:0] tf2 c / / t2 th2[7:0] rcap2l [7:0] rcap2h [7:0] ffh ffh exf2 t2ex pin interrupt 18 MPC89X54A data sheet megawin
baud-rate generator mode (brg) timer2 can be configured to generate various baud-rate. bit tclk and/or rclk in t2con allow the serial port transmit and receive baud rates to be derived from either timer1 or timer2. when tclk=0, timer1 is used as the serial port transmit baud rate generator. when tclk=1, timer2 is used as the serial port transmit baud rate generator. rclk has the same effect for the serial port baud rate. with these two bits, the serial port can have different receive and transmit baud rates ? one generated from timer1 and the other from timer2. in brg mode, timers is operated very like aut o-reload up-only mode except that the t2ex pin cannot control reload. an overflow on timer2 will load rcap2h, rcap2l contents onto timer2, but tf2 will not be set. a 1-to-0 transiti on on p2ex pin can set exf2 to request interrupt service if exen2=1. the baud rate in uart mode1 and mode3 are determined by timer2?s overflow rate given below: timer2 overflow rate 16 baud rate (counting t2ex) = oscillator frequency [32 x [65536 ? (rcap2h, rcap2l) ] ] baud rate = (as a timer) tl2[7:0] th2[7:0] rcap2l[7:0] rcap2h[7:0] ?1? ?0? ?1? ?0? 2 ?0? ?1? timer1 overflow 16 16 rx clock tx clock smod rclk tclk timer2 interrupt t2ex pin exen2 exf2 0 1 tr2 0 1 osc/12 t2 pin c//t2 megawin MPC89X54A data sheet 19
interrupt there are eight interrupt sources available in MPC89X54A. each interrupt source can be individually enabled or disabled by setting or clearing a bit in the sfr named ie . this register also contains a global disable bit ( ea ), which can be cleared to disable all interrupts at once. each interrupt source has two corresponding bits to represent its priority. one is located in sfr named iph and the other in ip/xicon register. higher-priority interr upt will be not interrupted by lower-priority interrupt request. if two interrupt r equests of different priority levels are received simultaneously, the request of higher priority is se rviced. if interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced. the following table shows the internal po lling sequence in the sa me priority level and the interrupt vector address. source vector address priority within level external interrupt 0 03h 1 (highest) timer 0 0bh 2 external interrupt 1 13h 3 timer1 1bh 4 serial port 23h 5 timer2 2bh 6 external interrupt 2 33h 7 external interrupt 3 3bh 8 the external interrupt /int0, /in t1, /int2 and /int3 each can be either level-activated or transition-activated, depending on bits it0 and it1 in sfr tcon , it2 and it3 and xicon . the flags that actually generate these interrupts are bits ie0 and ie1 in tcon , ie2 and ie3 in xicon . when an external interrupt is generated, the flag that generated it is cleared by the hardware. when the service routine is vectored to only if the interrupt wa s transition ?activated , and then the external requesting source controls the r equest flag, rather than the on-chip hardware. the timer0 and timer1 interrupts are generated by tf0 and tf1 , which are set by a rollover in their respective timer/counter registers in most cases. when a timer interrupt is generated, the flag, which generated it, is cleare d by the on-chip hardware as soon as the service routine is vectored to. the serial port interrupt is generated by the logical or of ri and ti . neither of these flags is cleared by hardware when the service routine is vectored to. the service routine should poll ri and ti to determine which one to request service and it will be cleared by software. the timer2 interrupt is generated by the logical or of tf2 and exf2 . just the same as serial port, neither of these flags is cleared by har dware when the service routine is vectored to. all of the bits that generate interrupts can be se t or cleared by software, and it has the same 20 MPC89X54A data sheet megawin
impact as done through by hardware. in other words, interrupts or pending interrupts can be generated or canceled in software. the following content describes several sfr related to interrupt mechanism. sfr: ie ( interrupt enabling ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ea et2 es et1 ex1 et0 ex0 ea : global disables all interrupts when cleared. et2 : when set, enables timer2 interrupt. es : when set, enables the serial port interrupt. et1 : when set, enables timer1 interrupt. ex1 : when set, enables external interrupt 1. et0 : when set, enables timer 0 interrupt. ex0 : when set, enables external interrupt 0. sfr: ip ( interrupt priority low ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - pt2 ps pt1 px1 pt0 px0 pt2 : if set, set priority fo r timer2 interrupt higher ps : if set, set priority for serial port interrupt higher pt1 : if set, set priority fo r timer1 interrupt higher px1 : if set, set priority for external interrupt 1 higher pt0 : if set, set priority fo r timer0 interrupt higher px0 : if set, set priority for external interrupt 0 higher sfr: iph ( interrupt priority high ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 px3h px2h pt2h psh pt1h px1h pt0h px0h px3h : if set, set priority for ex ternal interrupt 3 highest px2h : if set, set priority for ex ternal interrupt 2 highest pt2h : if set, set priority for timer2 interrupt highest psh : if set, set priority for serial port interrupt highest pt1h : if set, set priority for timer1 interrupt highest px1h : if set, set priority for ex ternal interrupt 1 highest pt0h : if set, set priority for timer0 interrupt highest px0h : if set, set priority for ex ternal interrupt 0 highest megawin MPC89X54A data sheet 21
ip (or xicon) and iph are combined to form 4-level priority interrupt as the following table. priority {iph.x , ip.x} level 11 1 (highest) 10 2 01 3 00 4 sfr: xicon ( external interrupt control ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 px3 ex3 ie3 it3 px2 ex2 ie2 it2 px3 : if set, set priority for ex ternal interrupt 3 higher ex3 : if set, enables external interrupt 3. ie3 : interrupt 3 edge flag. sets by hardware when external interrupt edge detected. cleared when interrupt processed. it3 : interrupt 3 type control bit. set/ cleared by software to specified falling edge/low level triggered interrupt. px2 : if set, set priority for ex ternal interrupt 3 higher ex2 : if set, enables external interrupt 2. ie2 : interrupt 2 edge flag. sets by hardware when external interrupt edge detected. cleared when interrupt processed. it2 : interrupt 2 types control bit. set/cleared by soft ware to specify falling edge/low level triggered interrupt. watchdog timer 8-bit pre-scalar timer 15-bit wdt ps0 ps1 ps2 reset 8 enw clk/12 clrw idle widl 22 MPC89X54A data sheet megawin
sfr: wdtcr ( watchdog timer control ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - enw clrw widl ps2 ps1 ps0 enw : enable wdt while it is set. enw cannot be cleared by firmware. 1: = enable watchdog timer, 0: = does not use watchdog timer clrw : clear wdt to recount while it is set. hardware will automatically clear this bit. widl : set this bit to disable wdt generating reset even though the c is in idle mode. {ps2, ps1, ps0} : select the pre-scalar output. { 0, 0, 0 }: = set the pre-scaling value 2 { 0, 0, 1 }: = set the pre-scaling value 4 { 0, 1, 0 }: = set the pre-scaling value 8 { 0, 1, 1 }: = set the pre-scaling value 16 {1 , 0, 0 }: = set the pre-scaling value 32 { 1, 0, 1 }: = set the pre-scaling value 64 { 1, 1, 0 }: = set the pre-scaling value 128 { 1, 1, 1 }: = set the pre-scaling value 256 serial io port (uart) the serial port of MPC89X54A is duplex. it can transmit and receive simultaneously. the receiving and transmitting of the serial port share the same sfr sbuf , but actually there are two sbuf registers implemented in the chip, one is for transmitting and the other is for receiving. the serial port can be operated in 4 different modes. mode 0 generally, this mode purely is used to ex tend the i/o features of this device. operating under this mode, the device receives the serial data or transmits the serial data via pin rxd, while there is a clock stream shifted vi a pin txd which makes convenient for external synchronization. an 8-bit data is serially trans mitted/received with lsb first. the baud rate is fixed at 1/12 the os cillator frequency. mode1 a 10-bits data is serially transmitted through txd or received through rxd. the frame data includes a start bit ( 0 ), 8 data bits and a stop bit ( 1 ). after the receiving, the device will keep the stop bit in rb8 which from srf scon . baud rate (for mode 1) = 2 smod 32 (timer-2 overflow rate) 16 or = x (timer-1 overflow rate) megawin MPC89X54A data sheet 23
mode2 an 11-bit data is serially transmitted through txd or received through rxd . the frame data includes a start bit ( 0 ), 8 data bits, a programmable 9th bit and a stop bit (1). on transmit, the 9th data bit comes from tb8 in sfr scon . on receive, the 9th data bit goes into rb8 in scon . the baud rate is programmable, and permitted to be set either 1/32 or 1/64 the oscillator frequency. baud rate (for mode 2) = 2 smod 64 x f osc mode3 mode 3 is the same as mode 2 except the baud rate is variable. baud rate (for mode 3) = 2 smod 32 (timer-2 overflow rate) 16 or = x (timer-1 overflow rate) in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiat ed in mode 0 by the condition ri = 0 and ren = 1 . reception is initiated in the other modes by the incoming start bit with 1 -to- 0 transition if ren = 1 . there are several sfr related to serial port configuration described as following. sfr: scon ( serial port control ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 sm0/fe sm1 sm2 ren tb8 rb8 ti ri fe : frame error bit. this bit is set by the receiver wh en an invalid stop bit is detected. the fe bit is not cleared by valid frames, but should be cleared by software. the smod0 (pcon.6) bit must be set to enable access to the fe bit. { sm0, sm1 } : used to set operating mode of the serial port. it is enabled to access by clearing smod0. { 0, 0 } := set the serial port operate under mode 0 { 0, 1 } := set the serial port operate under mode 1 { 1, 0 } := set the serial port operate under mode 2 { 1, 1 } := set the serial port operate under mode 3 24 MPC89X54A data sheet megawin
sm2 : enable the automatic address recognition feature in mode 2 and 3. if sm2 = 1 , ri will not be set unless the received 9th data bit is 1, indicating an address, and the received byte is a given or broadcast address. in mode1, if sm2=1 then ri will not be se t unless a valid stop bit was received, and the received byte is a given or broadcast address. ren : enable the serial port reception. 1 := enable 0 := disable tb8 : the 9th data bit, which will be transmitted in mode 2 and mode 3. rb8 : in mode 2 and 3, the received 9th data bit will go into this bit. ti : transmit interrupt flag. after a transmit has been finished, the hardware will set this bit. ri : receive interrupt flag. after reception has been finished, the hardware will set this bit. sfr: sbuf ( serial port buffer register ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 (data to be transmitted or received data) automatic address recognition there is an extra feature makes the device convenient to act as a master, which communicates to multiple slaves simultaneously. it is really automatic address recognition . there are two sfr saddr and saden implemented in the device. the user can read or write both of them. finally, the hardware will make use of these two sfr to ?generate? a ?compared byte?. the formula specifies as following. bit[ i ] of compared byte = ( saden [ i ] == 1 )? saddr [ i ] : x for example: set saddr = 11000000b set saden = 11111101b ? the achieved ?compared byte? will be ?110000x0? ( x means don?t care) for another example: set saddr = 11100000b set saden = 111110 10b ? the achieved ?compared byte? will be ?11100x0x? after the generic ?compared byte? has been worked out, the MPC89X54A will make use of this byte to determine how to set the bit ri in sfr scon . normally, an uart will set bit ri whenever it has done a byte rece ption; but for the uart in the MPC89X54A, if the bit sm2 is set, it will set ri according to the following formula. ri = (sm2 == 1) && (sbuf == compared byte ) && (rb8 == 1) megawin MPC89X54A data sheet 25
in other words, not all data reception will respond to ri, while specific data does. by setting the saddr and the saden, the user can filter out those data byte that doesn?t like to care. this feature brings great help to reduce software overhead. the above feature adapts to the serial port when operated in mode1, mode2, and mode3. dealing with mode 0, the user can ignore it. frame error detection a missing bit in stop bit will set the fe bit in the scon register. the fe bit shares the scon bit 7 with sm0 and its actual function for scon.7 is determined by smod0 ( pcon.6 ). if smod0 is set, scon.7 functions as fe , otherwise functions as sm0 . when used as fe bit, it can only be cleared by software. reset the reset pin is used to reset this device. it is connected into the device to a schmitt trigger buffer to get excellent noise immunity. any positive pulse from reset pin must be kept at least two-machine cycle, or the device cannot be reset. power saving mode and pof there are two power saving modes which are se lectable to drive the MPC89X54A to enter power-saving mode. 1. idle mode the user can set the bit pcon.0 to drive this chip entering idle mode. in the idle mode, the internal clock is gated off to the cpu, but not to the interrupt, timer and serial port functions. there are two ways to terminate the idle. activation of any enabled interrupt will cause pcon.0 to be cleared by hardware to terminating the idle mode. the interrupt will be serviced, and following reti, the next instruction to be execut ed will be performed right after the instruction that causes the device entering to idle mode. another way to wake-up from idle is to pull reset pin high to generate internal hardware reset. 26 MPC89X54A data sheet megawin
2. power-down mode the user can set the bit pcon.1 to drive this chip entering power-down mode. in the power-down mode, the on-chip oscillator is stopped. the conten ts of on-chip ram and sfrs are maintained. the power-down mode can be woken- up by either hardware reset or /int0 , /int1 , /int2 and /int3 external interrupts. when it is woken-up by reset pin, the program will execute from the address 0x0000, and be carefully to keep reset pin active for at least 10ms in order to get a stable clock while waking up this chip from power-down mode. if it is woken-up from i/o, the program will jump to related interrupt service routine. to use i/o wa ke-up, interrupt-related registers have to be programmed accura tely before power-down is entered. pay attention to add at least one ?nop? instruction subsequent to the power-down instruction if i/o waken-up is used. mode program memory ale psen port0 port1 port2 port3 idle internal 1 1 data data data data idle external 1 1 float data address data power-down internal 0 0 data data data data power-down external 0 0 float data data data pin status in idle mode and power-down mode 3. power-on flag (pof) the register bit in pcon.4 is set only by powe r-on action. system reset from watch-dog-timer, software reset and reset pin can not set this bit. it can be cleared by firmware. in system programming (isp) to develop a good program for isp function, the us er has to understand the architecture of the embedded flash. the embedded flash consists of 30 pages. each page contains 512 bytes. dealing with flash, the user must erase it in page unit before writing (programming) data into it. erasing flash means setting the content of that flash as ff h. two erase modes are available in this chip. one is mass mode and the other is page mode . the mass mode gets more performance, but it erases the entire flash. the page mode is something performance less, but it is flexible since it erases flash in page unit. unlike ram?s real-time operation, to erase flash or to write (program) flash often takes longer time to finish. megawin MPC89X54A data sheet 27
furthermore, it is a quite complex timing procedure to erase/program flash. fortunately, the MPC89X54A carried with convenient mechanism to help the user read/c hange the flash content. just filling the target address and data into several sfr, and triggering the built-in isp automation, the user can easily erase, r ead, and program the embedded flash and option registers or1 . there are several sfr designed to help t he user implement the isp functionality. sfr: ifd ( isp flash data register ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 (data to be written into flash, or data got from flash) ifd is the data port register for isp operation. the data in ifd will be wr itten into the desired address in operating isp write and it is the data win dow of readout in operating isp read. sfr: ifadrh ( isp flash address high ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 (high byte of the address pointing to flash memory) ifadrh is the high-byte address port for all isp modes. sfr: ifadrl ( isp flash address low ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 (low byte of the address pointing to flash memory) ifadrl is the low-byte address port for all isp modes. sfr: ifmt ( isp flash mode table ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 reserved mode selection mode selection to operate 0 0 0 standby 0 0 1 ap-memory read 0 1 0 ap-memory/data-flash program 0 1 1 ap-memory/data-flash page erase 1 1 1 or1 memory erase (ifadrl[0]=1). 1 0 1 or1 memory read ( ifadrl[0] =1) 1 1 0 or1 memory program ( ifadrl[0] = 1) note : or0 cannot be changed by isp operation. it can be accessed only by writer. only or1 can be changed by isp program. 28 MPC89X54A data sheet megawin
sfr: scmd ( sequential command data register for isp ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 isp-command (device id) scmd is the command port for triggering isp activity. if scmd is filled with sequential 46h, b9 h and if ispcr.7 = 1, isp activity will be triggered. when this register is read, the device id of MPC89X54A will be returned (2 bytes). the msb byte of did is f1 h and lsb byte 04 h. ifadrl[0] is used to sele ct high/low byte of did. sfr: ispcr ( isp control register ): bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 ispen swbs swrst - - wait ispen : isp function enabling bit 0 : = disable isp program to change flash 1 : = enable isp program to change flash swbs : secondary booting program selecting 0: = boot from main-memory. 1: = boot from isp memory. swrst : software reset trigger 0: = no operation 1: = generate software system reset. it will be cleared by hardware automatically. notice : software reset actions could reset other sfr, but it never influences bits ispen and swbs. the ispen and swbs only will be reset by power-up action, not software reset. wait : waiting time selection while the flash is busy. cpu wait time (machine cycle) ispcr[2:0] page erase pr ogram read recommended system clock 0 0 0 43769 240 43 40m 0 0 1 21885 120 22 20m 0 1 0 10942 60 11 10m 0 1 1 5471 30 6 5m procedures demonstrating isp function ifmt xxxxx 011 b /* choice page-erasing command */ ispcr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 10942 mc; assumed 10m x?s*/ ifadrh (page address high byte) /* specify the address of the page to be erased */ ifadrl (page address low byte) scmd 46 h /* trig isp activity */ scmd b9 h (cpu progressing will be hold here ) (cpu continues) erase a specific flash page megawin MPC89X54A data sheet 29
ifmt xxxxx 010 b /* choice byte-programming command */ ispcr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 60 mc; assumed 10m x?s*/ ifadrh (address high byte) /* specify the address to be programmed */ ifadrl (address low byte) ifd (byte date to be written into flash) /* prepare data source */ scmd 46 h /* trig isp activity */ scmd b9 h (cpu progressing will be hold here) (cpu continues) program a byte into flash ifmt xxxxx 001 b /* choice byte-read command */ ispcr 100xx010 b /* set ispen=1 to enable flash change. set wait=010, 11 mc; assumed 10m x?s*/ ifadrh (address high byte) /* specify the address to be read */ ifadrl (address low byte) scmd 46 h /* trig isp activity */ scmd b9 h (cpu progressing will be hold here) (cpu continues and currently ifd contain the desired data byte ) read a byte from flash booting program entrance the MPC89X54A boots according to the following rule. system will boot from normal ap program else system will boot from isp program if ( hwbs == 0 ) && ( { ispas1 , ispas0 } { 1, 1 }) above rule is adaptive only for power-up procedure, while not software reset. switching from isp program to ap program the device permits the user normally start running the ap program as soon as the isp program has finished updating the flash content. just progra m an instruction at the tail of isp program as ispcr 001 x xxxx b 30 MPC89X54A data sheet megawin
which disables flash-writing authority, set swbs 0 , and trigger a software reset. after that, the system will be reset (not powered- up), and the system will refer to swbs to startup from ap program entrance. for pow er-up procedure, the hwbs will be referred to decide the program entrance, but for software reset, swbs will be referred to. switch to the isp program from ap program the device also permits the user program switches directly to the isp pr ogram. just program an instruction in the ap program as ispcr x11 x xxxx b which sets swbs 1 to direct the device boot from ap program, and trigger a software reset. after that, the system will be reset (not power ed-up), and the system will refer to swbs to startup from isp program entrance. in-application program the in-application program feature is designed for user to read/write nonvolatile data flash . it may bring great help to store parameters those should be independent of power-up and power-done action. in other words, the user can store data in data flash memory, and after shutting down the mcu and rebooti ng the mcu, user still can get t he original value, which had stored in. the user can program the data flash according to the same way as isp program, and gets deeper understanding related to sfr ifd, ifadrl, ifadrh, ifmt, scmd, and ispcr . the data flash can be programmed by the ap program as well as the isp program. the isp program may program the ap memory and data flash , while the ap program may program the data flash but not the isp memory. if the ap program desires to change the isp memory associated with specific addre ss space, the hardware will ignore it. note : even the users do not need isp space, t he or0[5:4] still needs to be programmed with {10} if iap data flash is desired. in other words, the maximum available size in data flash for iap operation is 46k bytes. megawin MPC89X54A data sheet 31
note for other sfr sfr: auxr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - - - - - eram ao eram : define if hide the expanded ram, so to access to the external ram 0 : = the internal auxiliary ram access is enabled 1 : = the internal auxiliary ram access is disabled. t he movx instructions always direct to external ram. ao : 0 : = ale is emitted at a constant rate of 1/6 the o scillator frequency for 12t mode, and at a constant rate of 1/3 the oscillator frequency for 6t mode 1 : = ale is active only during access to external memory for both movc and movx sfr: auxr1 bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 - - - - gf2 - - dps gf2 : general purpose flag dps : data pointer switch 0 : = make the data pointer-0 active 1: = make the data pointer-1 active 32 MPC89X54A data sheet megawin
absolute maximum rating (mpc89e54a) parameter rating unit ambient temperature under bias -55 ~ +125 c storage temperature -65 ~ + 150 c voltage on any port i/o pin or rst with respect to ground -0.5 ~ vcc + 0.5 v voltage on vcc with respect to ground -0.5 ~ +6.0 v maximum total current through vcc and ground 500 ma maximum output current sunk by any port pin 40 ma *note: stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. this is a stress rating only and function al operation of the devices at those or any other conditions above those indicated in the operation listings of this spec ification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics (mpc89e54a) vss = 0v, ta = 25 and 12 clocks per machine cycle ,unless otherwise specified specification symbol parameter test condition min. typ. max. unit v il1 input low voltage (p0, 1,2,3,4) vcc=5.0v 0.8 v v il2 input low voltage (reset) vcc=5.0v 1.6 v v ih1 input high voltage (p0, 1, 2, 3, 4,ea) vcc =5.0v 2.0 v v ih2 input high voltage (reset) vcc=5.0v 3.0 v i ol1 sinking current for output low (p1, p2, p3, p4) vcc=5.0v 4 6 ma i ol2 sinking current for output low (p0, ale, psen) vcc=5.0v 8 12 ma i oh1 sourcing current for output high (p1, p2, p3, p4) vcc = 5.0v 150 220 ua i oh2 sourcing current for output high (ale, psen) vcc = 5.0v 14 20 ma i il logic 0 input current (p1,2,3,4) vpin=0v 18 50 ua i tl logic 1 to 0 transition current (p1,2,3,4) vpin=2.0v 270 600 ua i cc operating current @20mhz vcc=5.0v 30 ma i idle idle mode current @ 20mhz vcc=5.0v 7 ma i pd power down current vcc=5.0v 50 ua rrst internal pull-down resistance in reset 45k~116k ohm megawin MPC89X54A data sheet 33
absolute maximum rating (mpc89l54a) parameter rating unit ambient temperature under bias -55 ~ +125 c storage temperature -65 ~ + 150 c voltage on any port i/o pin or rst with respect to ground -0.3 ~ vcc + 0.3 v voltage on vcc with respect to ground -0.3 ~ +4.2 v maximum total current through vcc and ground 500 ma maximum output current sunk by any port pin 40 ma *note: stresses above those listed under ?absol ute maximum ratings? may cause permanent damage to the device. this is a stress rating only and function al operation of the devices at those or any other conditions above those indicated in the operation listings of this spec ification is not implied. exposure to maximum rating conditions for extended periods may affect device reliability. dc characteristics (mpc89l54a) vss = 0v, ta = 25 and 12 clocks per machine cycle ,unless otherwise specified specification symbol parameter test condition min. typ. max. unit v il1 input low voltage (p0, 1,2,3,4) vcc=3.3v 0.8 v v il2 input low voltage (reset) vcc=3.3v 1.5 v v ih1 input high voltage (p0, 1, 2, 3, 4,ea) vcc =3.3v 2.0 v v ih2 input high voltage (reset) vcc=3.3v 3.0 v i ol1 sinking current for output low (p1, p2, p3, p4) vcc=3.3v 2.5 4 ma i ol2 sinking current for output low (p0, ale, psen) vcc=3.3v 5 8 ma i oh1 sourcing current for output high (p1, p2, p3, p4) vcc = 3.3v 40 70 ua i oh2 sourcing current for output high (ale, psen) vcc =3.3v 8 13 ma i il logic 0 input current (p1,2,3,4) vpin=0v 8 50 ua i tl logic 1 to 0 transition current (p1,2,3,4) vpin=2.0v 110 600 ua i cc operating current @20mhz vcc=3.3v 30 ma i idle idle mode current @ 20mhz vcc=3.3v 6 ma i pd power down current vcc=3.3v 50 ua rrst internal pull-down resistance in reset 45k~116k ohm 34 MPC89X54A data sheet megawin
package dimension 40-pin pdip (MPC89X54Ae) megawin MPC89X54A data sheet 35
44-pin plcc (MPC89X54Ap) 36 MPC89X54A data sheet megawin
44-pin pqfp (MPC89X54Af) megawin MPC89X54A data sheet 37
revision history version date page description a3 2004/10 - reorganized a4 2004/11 p27 - added procedures demonstrating isp function a5 2005/01 - re-format - mark the reset pin resistance - remove the read-only limitation on sfr auxr - document on option register or1.7 - fix the baud-rate-computing formula for timer-1 a6 2005/01 - fix isp start address incorrect a7 2005/3/30 p6 - update pqfp-44 package shape a8 2005/6/14 p5, 8, 33 - modify pin /ea location for pdip and plcc package - modify bits definition for sfr pcon - absolute maximum rating a9 2006/09 p33, 34 - revises the possible operating temperature. a10 2007/03 p33 - modify the storage temperature a11 2007/12 p2 p34, 35 - add 2.7v requirement in flash write operation. - modify absolute maximum rating. a12 2008/12 - formatting 38 MPC89X54A data sheet megawin

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